1/10 june 1998 ? AN394 application note microwire eeprom common i/o operation within stmicroelectronics broad spectrum of different types of serial access eeprom pr oduct, the mi- crowire? family is based on a 4-wire interface. the four lines consist of: the clock input (c), the chip select input (s), the serial data input (d), and the serial data output (q). some microprocessor chips, such as sts microcontroller series, include an on-chip serial peripheral in- terface (spi). the microwire interface is ideally suited to use with these devices. however, the micro- wire eeprom devices can also be used with any general purpose microcontroller, provided that care is taken not to allow signal conflicts to result. this document discusses how to avoid such conflicts when tying the d and q lines together as a single bus. while commands, addresses or data are being shifted into the d serial input of the eeprom device, the q output is held in the high impedance state. it should be possible, therefore, to tie the d and q pins to- gether to provide a common d/q bus, as depicted in figure 1. the device can, indeed, operate correctly in this configuration, provided that appropriate design rules are followed. the potentially troublesome situations are during commands which activate the q output (such as read,write, erase, wral and eral). this document considers these cases, and recommends the most conservative solution to each problem. in order to provide the designer with a safe design guide, all calculations are based on worst case values, as found in the data sheets for these eeprom devices. figure 1. typical application of the common-d/q approach read instruction the d driver and the q receiver, in figure 1, can be discrete logic, or part of a microcontroller i/o port, or any equivalent circuitry. the read command and its address bits are clocked into the chip, through the d pin, on the rising edges of the c clock. each bit must be kept valid for a minimum hold time (tdvch) as specified in the data sheet for the memory device. the device holds the q pin in the high impedance state during most of the input operation. however, as figure 2 shows, the q pin is taken out of this state at the eeprom device d q data in driver enable (active low) common d/q bus data out q receiver clock in chip select in cs d driver ai02419
AN394 - application note 2/10 start of the last address bit (a0) of the instruction (signalled by the rising edge of c), and starts to output the leading zero that precedes the 16-bit data string. the data sheets specify the maximum delay (tchql) between the rising edge of c and the leading zero data bit. figure 2. timing sequence for a read instruction since the d driver must remain enabled with the a0 bit for a minimum of tdvch (the hold time), a bus conflict occurs whenever the a0 bit is a 1, as it would be for all odd addressed registers). the conse- quences are: C a low impedance path is created between vcc and ground through the d driver and the on-chip q output buffer (as depicted in figure 3). this short-circuit may produce glitches on the power supply which can disturb all the circuits on the board. C the logic level on the d/q bus is not well-defined: the potential divider chain, so created, can end up producing a voltage level anywhere between vcc and 0 v. thus access to the odd addressed registers will probably be impossible. figure 3. short-circuit created between vcc and ground ai02420 d 1 bus conflict q c s 1 0 a5 a4 a3 a2 a1 a0 0 d15 d14 d13 d12 d11 d10 d9 high impedance ai02424 eeprom device d q a0="1" common d/q bus d driver low impedance path output buffer v cc
3/10 AN394 - application note this problem can be avoided by inserting a current limiting resistor in the current sink path. figure 4 shows some possible locations for this resistor. however, the best location is between the q output and the d/q bus for the following reasons: C during the overlap time, only the d driver is providing useful information. the q driver simply outputs a constant zero. by placing the resistor in this position, the d driver overrides the q driver at setting the logic level on the d/q bus, thereby allowing the last address bit to be presented on the d pin for the specified hold time (tdvch). C the r resistor slows down the propagation time of the q output signals on the d/q bus, as discussed later in this document. in this position, the resistor only slows down the transmission of the 16 bits of data during a read operation. if r were in series with the d driver, all operations would be slowed down. figure 4. possible locations for the current limiting resistor the r resistor does not have any effect as long as q is in its high impedance state. during the execution of a read instruction, r sinks some current from the d driver during the short overlap time. then the d driver is disabled and q output takes control of the d/q bus through the r resistor. because of the bus capacitance, c, the signals are distorted, as shown in figure 5 (on the next page): the rising and falling edges of the q output are transformed into exponential curves whose shape depends on the time constant rc. ai02421 eeprom device d q a0="1" recommended location d driver output buffer v cc r r r not recommended locations (if d driver is an open collector type)
AN394 - application note 4/10 figure 5. exponential charge and discharge of the bus capacitance as a consequence, the logic level on the d/q bus is not stable until some time after the rising edge of the c clock. the delay in reading the bus should be at least 3xrc. in a typical data sheet for a 5 v device, voh(min) = 2.4 v and vol(max) = 0.4 v, so giving a voltage swing of 2 v. using the 3xrc approximation, the d/q bus levels will be: C logical 1 = 2.3 v minimum after a delay of 3xrc C logical 0 = 0.5 v maximum after the c rising edge it might be necessary to reduce the c clock frequency, when shifting the 16 data bits out from the eep- rom during a read operation, by an amount that is directly related to the rc time constant of the d/q bus. all other operations can be performed at the nominal clock rate. figures 6, 7, 8 show some experimental examples, plotted from the oscilloscope, with different values of r and c. in the last example, the maximum clock frequency is: 1/(3xrc) = 100 khz, assuming that the d/ q bus is sampled by the q receiver circuitry just before the rising edge of the c clock. ai02422 0 rc 2xrc 3xrc 63% rc = time constant 86% 95% 0 rc 2xrc 3xrc 5% 13% 37% % of the voltage swing
5/10 AN394 - application note figure 6. oscilloscope plot, r = 10 k w , c = 100 pf, rc = 1 m s figure 7. oscilloscope plot, r = 5 k w , c = 100 pf, rc = 500 ns ai02425 5v 10 m s c clock d/q bus q output d driver enable (1 = disabled) ao bit is '1' q output a '0' bit d/q bus is now driven by q d driver is disabled here
AN394 - application note 6/10 figure 8. oscilloscope plot, r = 10 k w , c = 330 pf, rc = 3.3 m s in order to avoid over reducing the clock frequency, the following techniques can be used to minimize the r and c values: n to minimize the bus capacitance: C the eeprom device should be position as close as possible to the d-driver/q-receiver circuitry (the ca- pacitance is proportional to the surface area of the bus line). C as few devices as possible should share the d/q bus (the capacitance is proportional to the number of input gates connected to the bus). n to minimize the resistor value: C find, from the data sheet, the maximum current that the d driver can source, and divide this value into the value of vcc. C find the maximum transient current that the power supply can source without glitches being introduced on to the power lines, and divide this value into the value of vcc. C it is up to the designer to decide the best trade-off, based upon his specific applications requirements, but the resistor value should not be less than the higher of the two values calculated above. interface with cmos circuits the microwire eeprom specification makes these devices compatible with ttl input/output levels. when interfacing these devices to cmos circuits, however, some precautions must be taken, to ensure the correct interpretation of the logic levels. since the output-high level is close to vcc, and the output-low level is close to 0 v, there are no difficulties in driving the d, s and c inputs of the eeprom devices. for the q output, though, the minimum output-high level is specified as being 2.4 v, which is lower than the minimum input-high level of cmos (3.5 v for vcc = 5 v). a common practice is to connect a pull-up resistor, rp, between the q output and vcc. this solution works well when d and q are separate. however, it raises some difficulties when d and q are tied together. ai02427 5v c clock d/q bus q output d driver enable (1 = disabled) 10 m s
7/10 AN394 - application note when the q output is at a zero level (vol= 0.4 v), during the overlap period, the r and rp resistors form a potential divider chain, as shown in figure 9. rp must have a resistance greater than 5 times that of r. this means that the zero level on the d/q bus is: 0.4 v + (5 v -0.4 v) x r / (r + rp) = 1.17 v. although this value is 330 mv below the 1.5 v maximum input-low level for cmos, it does mean losing the wide noise margin that is traditionally associated with the cmos specification. figure 9. d/q bus configuration with pull-up resistor (rp) for a high to low transition, the q on-chip output buffer has to discharge the bus capacitance through the r resistor and to sink some current from vcc through the rp resistor. the new time constant, when com- pared to that calculated earlier in this document, is reduced by 17%, because of the parallel combination of r and rp. however, the steady low level is not 0.4 v, as had been assumed for ttl levels, but 1.17 v, as calculated above for rp = 5xr. despite this smaller time constant, the voltage swing between high and low is greater in this case, as described later in this document, so it is advisable to keep the same delay (3xrc) between the c clock rising edge and the first sampling of the data line. a greater problem is faced during the low to high transition, though. at first, the bus capacitance is charged by the q output through r, and from the vcc power supply via rp, again leading to a time constant for rp connected in parallel with r. but once the d/q bus reaches the q output voltage level, the q on-chip buffer automatically turns off, and the rp resistor remains the only contributor to the charge of the bus capaci- tance. this results in a much higher time constant: rpxc =5xrc. for the worst case output-high level for q (voh= 2.4 v), combined with the minimum input-high level for cmos, the charging delay, after the q driver cuts out, needs to be at least 0.55xrpc: that is, 2.75xrc. this is still assuming vcc = 5 v, and allowing for a noise margin of 300 or 400 mv. as a result, the minimum delay between the rising edge of c and the sampling of the d/q bus should be 2 or 3 times longer than the one we have found for the ttl levels (without rp), and the clock frequency must be reduced accordingly. (a typical oscilloscope plot is shown in figure 10). it is possible to avoid this situation by using a ttl-compatible cmos device as the q receiver circuit, and thereby to remove the need for the rp resistor. suitable devices include: n members of the 74hctxxx family n a cmos microcontroller that provides an option for ttl input levels on its i/o ports, such as the st9 series. ai02423 eeprom device d q data in d driver (cmos) output buffer r r p v cc driver enable (active low) data out q receiver (cmos)
AN394 - application note 8/10 figure 10. oscilloscope plot, r = 10 k w , c = 100 pf, rp = 50 k w programming mode: acknowledgement of ready/busy status during a self-timed programming cycle, microwire eeprom devices use the q output to indicate the ready/busy status of the chip. this occurs during the execution of commands such as: write, erase, wral and eral. the self-timed programming cycle begins with the falling edge of s, at the end of a programming com- mand. the s pin must be kept low for a minimum of tslsh (as described in the data sheet). the q output remains in its high impedance state as long as s is low. if s is brought high for clocking-in a new command, q comes out of its high impedance state, and indicates the ready/busy status of the chip (0 = busy, 1 = ready). figure 11. acknowledgement of the ready/busy signal on the q output ai02428 5v c clock d/q bus q output d driver enable (1 = disabled) 10 m s ai02429 5v c clock d/q bus d driver enable (1 = disabled) 10 m s
9/10 AN394 - application note in applications where d and q are tied together, this may again create bus conflicts. therefore, it is rec- ommended that this status signal be cancelled as soon as possible: this can be achieved very simply by applying a single clock pulse on the c input while s is high, as depicted in figure 11. the operation is scheduled as follows: C shift the write command into the chip C bring s low for the minimum period of tslsh C bring s high C monitor the d/q bus until a high level (ready) is detected Cclock c once C bring s low C the chip is now ready to accept the next instruction it should also be noted that, on power-up, the ready/busy status be initially in the active state. therefore, it is recommended to clock c once (with s = 1) prior to the issue of the first command. improving on the calculations in this document this document has discussed how microwire devices can be used in a configuration in which the d and q lines are tied together as a single bus. for safety, and for generality, the worst case and most con- servative conditions have been assumed in all calculations. in particular circumstances, however, it might be possible for the designer to do better than this. in the designers own particular application, it might be reasonable to rule out some worst-case situations as nev- er occurring, and to adapt the calculations accordingly.
AN394 - application note 10/10 if you have any questions or suggestions concerning the matters raised in this document, please send them to the following electronic mail address: apps.eeprom@st.com please remember to include your name, company, location, telephone number and fax number. information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. ? 1998 stmicroelectronics - all rights reserved the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. stmicroelectronics group of companies australia - brazil - china - france - germany - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapor e - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a.
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